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1.

The Improved RISC-V Specification (latest WIP draft)

5 points

2 years ago

2.

Show HN:Interactive RISC-V CPU Visualizer (Sequential and Pipelined) (mostlykiguess.github.io)

4 points

7 months ago

3.

Show HN: Miralis – a RISC-V virtual firmware monitor (github.com/CharlyCst)

4 points

a year ago

4.

GNU toolchain for RISC-V including GCC (github.com/riscv-collab)

178 points

3 years ago

5.

RISC-V J extension – Instructions for JITs (github.com/riscv)

137 points

4 years ago

6.

F# RISC-V Instruction Set formal specification (github.com/mrLSD)

134 points

3 years ago

7.

Show HN: v8-riscv — Port of JavaScript V8 engine to RISC-V (github.com/v8-riscv)

123 points

5 years ago

8.

F# RISC-V Instruction Set Formal Specification (github.com/mrLSD)

122 points

7 years ago

9.

RISC-V formal spec public review (github.com/riscv)

116 points

7 years ago

10.

RISC-V Software Ecosystem Overview (github.com/riscv)

83 points

6 years ago

11.

RISC-V Scalar Cryptography Extension reaches public review (github.com/riscv)

78 points

5 years ago

12.

Show HN: RISC-V disassembler in 200 lines of C (github.com/andportnoy)

29 points

6 years ago

13.

RISC-V Server Platform Spec Ratified (github.com/riscv-non-isa)

17 points

a month ago

14.

Show HN: #AlphanumericShellcoding, alphanumeric shellcodes on RISC-V [DEFCON'27] (github.com/RischardV)

7 points

7 years ago

15.

Show HN: A straightforward RISC-V 32-bit emulator (github.com/jawline)

5 points

2 years ago

16.

RISC-V(RV32IM) emulator written in C (github.com/mirimmad)

5 points

3 years ago

17.

RISC-V Integrated Matrix Extension Release for Internal Review (github.com/riscv)

5 points

3 months ago

18.

RISC-V J extension: makes RISC-V a target for JIT/interpreted languages (github.com/riscv)

5 points

2 years ago

19.

RISC-V Vector Extension 1.0, frozen for public review (github.com/riscv)

5 points

5 years ago

20.

RISC-V Open Source Supervisor Binary Interface (github.com/riscv)

5 points

5 years ago

21.

A RISC-V assembler in Tcl (github.com/jbroll)

4 points

5 years ago

22.

RISC-V RVA23 and RVB23 v0.6 profiles released for Public Review (github.com/riscv)

3 points

2 years ago

23.

Librpmi: A RISC-V Platform Management Interface protocol implementation (github.com/riscv-software-src)

3 points

2 years ago

24.

Intel Labs darecreek: open-source RISC-V vector unit (currently under test) (github.com/IntelLabs)

3 points

3 years ago

25.

Boom: A high-performance open source RISC-V core (github.com/riscv-boom)

3 points

5 years ago

26.

Google RISCV-DV, An open-source instruction generator for RISC-V verification (github.com/google)

3 points

6 years ago

27.

RISC-V Software Ecosystem Overview (github.com/v8-riscv)

3 points

6 years ago

28.

List of RISC-V Cores, SoC platforms and SoC chips available (github.com/riscv)

3 points

6 years ago

29.

A Tour of the RISC-V ISA Formal Specification (github.com/rsnikhil)

3 points

6 years ago

30.

Verilog for all proposed RISC-V bitmanip instructions (github.com/riscv)

3 points

7 years ago