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1.
▲
Linux-Xlnx – The official Linux kernel from Xilinx
(github.com/Xilinx)
41 points
maydemir
4 years ago
16 comments
2.
▲
AMD VitisT Al Integrated Development Environment
(github.com/Xilinx)
3 points
andsoitis
9 months ago
discuss
3.
▲
Xilinx Vitis AI – New Development Stack for AI Inference on Xilinx FPGA and ACAP
(github.com/Xilinx)
2 points
KenanSulayman
6 years ago
discuss
4.
▲
Xilinx Virtual Cable – debug FPGA/SoC designs without a physical cable
(github.com/Xilinx)
1 point
unwind
11 years ago
discuss
5.
▲
The Nanotube Compiler and Framework
(github.com/Xilinx)
1 point
ashvardanian
3 years ago
discuss
6.
▲
An open source Xilinx Spartan 6 miniPCIe development board
(github.com/polysome)
92 points
polysome
11 years ago
45 comments
7.
▲
How to set up Xilinx Vivado for source control
(github.com/jhallen)
60 points
jhallenworld
7 years ago
23 comments
8.
▲
NeoApple2: A Port of the Apple2fpga Apple II Emulator to Xilinx FPGAs
(github.com/zf3)
54 points
syscall63
5 years ago
2 comments
9.
▲
PCIe Endpoint on Xilinx 7-Series FPGAs with PCIe_2_1 Hard Block and GTP
(github.com/regymm)
34 points
transpute
a year ago
discuss
10.
▲
Xilinx Virtex 7 FPGA bitstream has been reverse engineered
(github.com/SymbiFlow)
14 points
rwmj
8 years ago
1 comment
11.
▲
Python Tools for Xilinx Vivado FPGA Projects
(github.com/benreynwar)
4 points
craigjb
11 years ago
discuss
12.
▲
OpenXC7 – free and open source FPGA toolchain for AMD/Xilinx Series 7 chi
(github.com)
2 points
gjvc
a year ago
discuss
13.
▲
AIEBLAS: Open-Source Expandable BLAS Implementation for AMD/Xilinx Versal Device
(github.com/atlarge-research)
1 point
teleforce
2 years ago
discuss
14.
▲
System-Verilog Code for DDR4 Memory Controller with Xilinx Phy (2021)
(github.com/oprecomp)
1 point
peter_d_sherman
4 years ago
discuss
15.
▲
Xilinx Bitstream Format Library. Easily read .bit files from C programs
(github.com/wkoszek)
1 point
wkoszek
11 years ago
discuss
16.
▲
Launch HN: Tensil (YC S19) – Open-Source ML Accelerators
96 points
tdba
4 years ago
87 comments
17.
▲
Show HN: An efficient SRL32 (cascading shift registers) clock prescaler in VHDL
(gist.github.com)
2 points
VioletVillain
2 years ago
discuss
18.
▲
Show HN: A High-Performance CRC Hardware Generator in Bluespec SystemVerilog
(github.com/datenlord)
2 points
SandmanDZ
3 years ago
discuss