CRC is a mature and widely-adopted error-detecting technology, and there have been numerous hardware implementations of it. However, most existing hardware designs are either implemented using pure combinational logic or are only designed to process input data byte-by-byte serially, which results in extremely low throughput. Other designs targeting high-performance applications lack proper parameterization and only support some specific CRC configurations. Blue-crc aims to solve these problems by providing both high-throughput and well-parameterized CRC hardware implementation.

Main Features of Blue-CRC Complete CRC Configuration: the implementation supports complete CRC configuration parameters, including polynomial, initVal(the initial CRC value), finalXor(the result is xor’d with this value if desired), reflectData(if True, the input bit order is reversed), and reflectRemainder(if True, the result bit order is reversed).

Standard Interfaces: The input interface follows AxiStream protocol, with a parameterized data width. The output CRC result is guarded by the basic handshake protocol.

Parallel: The IP is designed to process multiple bytes per cycle.

Fully Pipelined: The implementation takes in raw data and produces results every cycle.

High Throughput: The implementation, configured with 256-bit input and 32-bit CRC output, runs at 500MHz on Xilinx xcvu9p FPGA.

Have a try? For BSV users, you can import our codes and instantiate CrcAxiStream interface in your design directly. Besides, we provide a script to generate custom Verilog CRC implementation automatically. If you are interested in high-performance CRC hardware acceleration, it’s worth giving it a try. We are also open to any recommendations for further improving our designs.

Link GitHub: https://github.com/datenlord/blue-crc

References: https://ieeexplore.ieee.org/abstract/document/5501903