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151.

JuiceVM: Smallest RISC-V Virtual Machine that can run Linux mainline kernel (github.com/juiceRv)

7 points

5 years ago

152.

BinSym: Symbolic execution for RISC-V machine code based on LibRISCV ISA model (github.com/agra-uni-bremen)

6 points

2 years ago

153.

CVA6 – an Application class 6-stage RISC-V CPU capable of booting Linux (github.com/openhwgroup)

6 points

3 years ago

154.

FreeBSD Adapted for Cheri-MIPS, Cheri-RISC-V, and Arm Morello (github.com/CTSRD-CHERI)

6 points

5 years ago

155.

Flute: RISC-V CPU, simple 5-stage in-order pipeline (github.com/bluespec)

6 points

7 years ago

156.

RISC-V Vector Extension for Integer Workloads: An Informal Gap Analysis (gist.github.com)

5 points

2 years ago

157.

Show HN: RISC-V Linux Terminal emulated via WASM (cartesi-machine.surge.sh)

5 points

3 years ago

158.

Show HN: Brainfuck to RISC-V JIT compiler written in Zig (github.com/evelance)

5 points

a year ago

159.

XiangShan (香山) is an open-source high-performance RISC-V processor project (github.com/OpenXiangShan)

5 points

4 years ago

160.

We Built UltrafastSecp256k1 Up to 51% Faster ECC Across x86,ARM64,and RISC-V

5 points

3 months ago

161.

MODPlayRISCV – Playing tracker Music on ultra-low-end RISC-V MCUs (github.com/cpldcpu)

5 points

7 months ago

162.

RVVM: RISC-V Virtual Machine (github.com/LekKit)

5 points

a year ago

163.

Release RP2350 and ESP32-C6 support, RISC-V native emitter, common TinyUSB code (github.com/micropython)

5 points

2 years ago

164.

Ettore: RISC-V virtual machine, written in Go (github.com/teivah)

5 points

2 years ago

165.

SERV – The SErial RISC-V CPU (github.com/olofk)

5 points

2 years ago

166.

A minimal operating system (2K LOC) on QEMU and a RISC-V board (github.com/yhzhang0128)

5 points

3 years ago

167.

core-v-wally: Configurable RISC-V Processor (github.com/openhwgroup)

5 points

3 years ago

168.

Show HN: C++17 RISC-V RV32/64/128 userspace emulator library (github.com/fwsGonzo)

5 points

4 years ago

169.

T-Head/Alibaba RISC-V CPU cores open sourced (github.com/T-head-Semi)

5 points

5 years ago

170.

OpenXiangShan, an open-source high-performance RISC-V processor project (github.com/OpenXiangShan)

5 points

5 years ago

171.

Rvemu: RISC-V Emulator written in Rust (browser and CLI) (github.com/d0iasm)

5 points

5 years ago

172.

Some Criticisms of RISC-V (gist.github.com)

5 points

7 years ago

173.

Opensouce RISC-V CPU core implemented in Verilog from scratch in one night (github.com/darklife)

4 points

a year ago

174.

SERV – The SErial RISC-V CPU (github.com/olofk)

4 points

peter_d_sherman

2 years ago

175.

Standalone C compiler/assembler/linker/Libc for x86-64/aarch64/riscv64/WASM (github.com/tyfkda)

4 points

a year ago

176.

RV64GC Emulator: A RISC-V Emulator developed in C++20 (github.com/bane9)

4 points

3 years ago

177.

MemPool: Many-core image processor based on RISC-V with Shared L1 cache (github.com/pulp-platform)

4 points

3 years ago

178.

PULPino: open-source microcontroller based on a 32-bit RISC-V core (github.com/pulp-platform)

4 points

10 years ago

179.

RVVM – RISC-V VM emulator (github.com/LekKit)

4 points

7 months ago

180.

Amiberry-Lite is an optimized Amiga emulator for ARM and RISC-V platforms (github.com/BlitterStudio)

4 points

8 months ago