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121.

ZipCPU – A small, lightweight, RISC soft core in Verilog (github.com/ZipCPU)

118 points

7 years ago

122.

T1: A RISC-V Vector processor implementation (github.com/chipsalliance)

117 points

a year ago

123.

Show HN: Anos – a hand-written ~100KiB microkernel for x86-64 and RISC-V (github.com/roscopeco)

115 points

2 months ago

124.

Jupiter: RISC-V Assembler and Runtime Simulator (github.com/andrescv)

112 points

7 years ago

125.

NanoKVM: Affordable, Multifunctional, Nano RISC-V IP-KVM (github.com/sipeed)

111 points

2 years ago

126.

Show HN: IDE for Learning RISC-V (github.com/TheThirdOne)

105 points

7 years ago

127.

An FPGA-friendly 32-bit RISC-V CPU implementation (github.com/SpinalHDL)

102 points

9 years ago

128.

VeriGPU: GPU in Verilog loosely based on RISC-V ISA (github.com/hughperkins)

101 points

4 years ago

129.

Open-source soft-core RISC-V SoC with gdb support (github.com/stnolting)

94 points

5 years ago

130.

A minimal operating system (2K LOC) on QEMU and a RISC-V board (github.com/yhzhang0128)

87 points

3 years ago

131.

SiFive open sources RISC-V chips (github.com/sifive)

85 points

10 years ago

132.

Glacial – Microcoded RISC-V core designed for low FPGA resource utilization (github.com/brouhaha)

78 points

peter_d_sherman

5 years ago

133.

ORCA – An implementation of RISC-V intended to target FPGAs (github.com/VectorBlox)

77 points

10 years ago

134.

The Ice-V: a simple, compact RISC-V RV32I implementation in Silice (github.com/sylefeb)

75 points

5 years ago

135.

Show HN: New RISC-V emulator for Computer Science education (github.com/gboncoffee)

71 points

2 years ago

136.

Multiplix, operating system kernel for RISC-V and AArch64 SBCs (github.com/zyedidia)

70 points

3 years ago

137.

Emuko: Fast RISC-V emulator written in Rust, boots Linux (github.com/wkoszek)

70 points

3 months ago

138.

Mojo-V: Secret Computation for RISC-V (github.com/toddmaustin)

66 points

7 months ago

139.

Show HN: A pipelined RISC-V processor written in VHDL (github.com/inforichland)

65 points

11 years ago

140.

Click-V: A RISC-V emulator built with ClickHouse SQL (github.com/SpencerTorres)

64 points

a year ago

141.

Adding custom RISC-V instructions to an open-source rv32 SoC (github.com/stnolting)

54 points

4 years ago

142.

PicoRV32 – A Size-Optimized RISC-V CPU (github.com/cliffordwolf)

53 points

11 years ago

143.

Geohot/twitchcore: A RISC-V core, first in Python, then in Verilog, then on FPGA (github.com/geohot)

51 points

5 years ago

144.

Show HN: I built a RISC-V emulator that runs DOOM (github.com/lalitshankarch)

50 points

a month ago

145.

Some Criticisms of RISC-V (gist.github.com)

41 points

DyslexicAtheist

7 years ago

146.

Show HN: Libriscv – RISC-V userspace emulator library (github.com/fwsGonzo)

40 points

4 years ago

147.

NEORV32: A tiny, embedded and free-of-charge open-source RISC-V SoC (github.com/stnolting)

40 points

4 years ago

148.

ArgoCD: Use of Risky or Missing Cryptographic Algorithms in Redis Cache (github.com/argoproj)

33 points

2 years ago

149.

Show HN: C++17 RISC-V RV32GC / RV64GC userspace emulator library (github.com/fwsGonzo)

31 points

6 years ago

150.

128-bit RISC-V assembler (github.com/fwsGonzo)

30 points

5 years ago