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31.

Librpmi: A RISC-V Platform Management Interface protocol implementation (github.com/riscv-software-src)

3 points

2 years ago

32.

Intel Labs darecreek: open-source RISC-V vector unit (currently under test) (github.com/IntelLabs)

3 points

3 years ago

33.

Boom: A high-performance open source RISC-V core (github.com/riscv-boom)

3 points

5 years ago

34.

Configuration object and YAML-based storage for Rails apps (github.com/RISCfuture)

3 points

15 years ago

35.

Google RISCV-DV, An open-source instruction generator for RISC-V verification (github.com/google)

3 points

6 years ago

36.

RISC-V Software Ecosystem Overview (github.com/v8-riscv)

3 points

6 years ago

37.

List of RISC-V Cores, SoC platforms and SoC chips available (github.com/riscv)

3 points

6 years ago

38.

A Tour of the RISC-V ISA Formal Specification (github.com/rsnikhil)

3 points

6 years ago

39.

Verilog for all proposed RISC-V bitmanip instructions (github.com/riscv)

3 points

7 years ago

40.

RISC-V journey thru containers and new projects (github.com/carlosedp)

3 points

7 years ago

41.

Ruby Dropbox gem (github.com/riscfuture)

3 points

16 years ago

42.

Need Suggestions for Riscv CPU (github.com/SHAOWEICHEN000)

2 points

a year ago

43.

Excellent Project Documentation (github.com/RISCfuture)

2 points

13 years ago

44.

Preliminary in-progress RISC-V "P" Extension (github.com/riscv)

2 points

a month ago

45.

RISC-V Architecture Profiles 0.5 (RVI20, RVA20 and RVA22) for Discussion (github.com/riscv)

2 points

4 years ago

46.

Digital Signatures on Risc0 (github.com/risc0)

2 points

4 years ago

47.

ELF Reader in Pure Tcl (github.com/jbroll)

2 points

5 years ago

48.

riscv-pk: RISC-V Proxy Kernel and Boot Loader (github.com/riscv)

2 points

6 years ago

49.

New open source F# RISC-V ISA formal specification and CPU simulation (github.com/mrLSD)

2 points

7 years ago

50.

Working draft of the proposed RISC-V V vector extension (github.com/riscv)

1 point

2 years ago

51.

RISC Zero MCP Server: Run Trustless and Verifiable Agentic Workflows (github.com/ronantakizawa)

1 point

10 months ago

52.

Concerns over mask register design in RISC-V Vector Extension v1.0 (github.com/riscv)

1 point

4 years ago

53.

Show HN: Random instruction generator for RISC-V processor verification (github.com/google)

1 point

5 years ago

54.

F# RISC-V Instruction Set Formal Specification (github.com/mrLSD)

1 point

7 years ago

55.

Application execution environment for statically-linked RISC-V ELF binaries (github.com/riscv)

1 point

7 years ago

56.

RISC vs. Cores and SoCs (github.com/riscv)

1 point

7 years ago

57.

Show HN: I integrated my from-scratch TCP/IP stack into the xv6-riscv OS (github.com/pandax381)

147 points

9 months ago

58.

Show HN: Porting xv6 to HiFive Unmatched board (github.com/eyengin)

26 points

5 months ago

59.

Show HN: Easier Setup for Stephen Marz's “RISC-V OS in Rust” Series (github.com/kaycebasques)

3 points

3 years ago

60.

Project Oberon 2013 on RISC-V (github.com/solbjorg)

140 points

5 years ago