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511.

Open source RISC-V implemented from scratch in one night (github.com/darklife)

272 points

8 years ago

512.

XiangShan – Open-source high performance RISC-V processor (github.com/OpenXiangShan)

270 points

a year ago

513.

Open-source high-performance RISC-V processor (github.com/OpenXiangShan)

262 points

3 years ago

514.

Lion: A formally verified, 5-stage pipeline RISC-V core (github.com/standardsemiconductor)

241 points

5 years ago

515.

Writing an OS in Rust to run on RISC-V (gist.github.com)

229 points

3 years ago

516.

Ariane RISC-V CPU – An open source CPU capable of booting Linux (github.com/openhwgroup)

210 points

6 years ago

517.

Open source RISC-V GPGPU (github.com/vortexgpgpu)

207 points

5 years ago

518.

A tiny C header-only RISC-V emulator (github.com/cnlohr)

205 points

4 years ago

519.

Octox: Unix-like OS in Rust inspired by xv6-riscv (github.com/o8vm)

190 points

3 years ago

520.

Show HN: RISC-V core written in 600 lines of C89 (github.com/mnurzia)

190 points

3 years ago

521.

Linux running inside a PDF file via a RISC-V emulator (github.com/ading2210)

183 points

a year ago

522.

Ariane RISC-V CPU (github.com/pulp-platform)

171 points

8 years ago

523.

Show HN: Minimax – A Compressed-First, Microcoded RISC-V CPU (github.com/gsmecher)

171 points

4 years ago

524.

Fast RISC-V-based scripting back end for game engines (github.com/fwsGonzo)

159 points

2 years ago

525.

A Verilog to Factorio Compiler and Simulator (Working RISC-V CPU) (github.com/ben-j-c)

154 points

2 months ago

526.

Western Digital SweRV RISC-V Core (github.com/chipsalliance)

153 points

6 years ago

527.

Ripes: Visual computer architecture simulator, assembly code editor for RISC-V (github.com/mortbopet)

151 points

3 years ago

528.

LuaJIT PR: Add Support for RISC-V 64 (github.com/LuaJIT)

146 points

2 years ago

529.

RVVM – The RISC-V Virtual Machine (github.com/LekKit)

140 points

3 years ago

530.

RVVM – RISC-V Virtual Machine (github.com/lekkit)

129 points

5 years ago

531.

A FPGA friendly 32 bit RISC-V CPU implementation (github.com/SpinalHDL)

121 points

a year ago

532.

IceStick Tutorial: experience FPGA design and RISC-V using $40 FPGA device (github.com/BrunoLevy)

119 points

6 years ago

533.

ZipCPU – A small, lightweight, RISC soft core in Verilog (github.com/ZipCPU)

118 points

7 years ago

534.

T1: A RISC-V Vector processor implementation (github.com/chipsalliance)

117 points

a year ago

535.

Show HN: Anos – a hand-written ~100KiB microkernel for x86-64 and RISC-V (github.com/roscopeco)

115 points

2 months ago

536.

Jupiter: RISC-V Assembler and Runtime Simulator (github.com/andrescv)

112 points

7 years ago

537.

NanoKVM: Affordable, Multifunctional, Nano RISC-V IP-KVM (github.com/sipeed)

111 points

2 years ago

538.

Show HN: IDE for Learning RISC-V (github.com/TheThirdOne)

105 points

7 years ago

539.

An FPGA-friendly 32-bit RISC-V CPU implementation (github.com/SpinalHDL)

102 points

9 years ago

540.

VeriGPU: GPU in Verilog loosely based on RISC-V ISA (github.com/hughperkins)

101 points

4 years ago