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331.

BinSym: Symbolic execution for RISC-V machine code based on LibRISCV ISA model (github.com/agra-uni-bremen)

6 points

2 years ago

332.

CVA6 – an Application class 6-stage RISC-V CPU capable of booting Linux (github.com/openhwgroup)

6 points

3 years ago

333.

De-risking custom technology projects (18F) (github.com/18F)

6 points

thibaut_barrere

5 years ago

334.

FreeBSD Adapted for Cheri-MIPS, Cheri-RISC-V, and Arm Morello (github.com/CTSRD-CHERI)

6 points

5 years ago

335.

Value at Risk (github.com/mnquants)

6 points

5 years ago

336.

Flute: RISC-V CPU, simple 5-stage in-order pipeline (github.com/bluespec)

6 points

7 years ago

337.

RISC-V Vector Extension for Integer Workloads: An Informal Gap Analysis (gist.github.com)

5 points

2 years ago

338.

Show HN: RISC-V Linux Terminal emulated via WASM (cartesi-machine.surge.sh)

5 points

3 years ago

339.

Ask HN: Why some stories rise while others go unnoticed?

5 points

9 years ago

340.

Show HN: Brainfuck to RISC-V JIT compiler written in Zig (github.com/evelance)

5 points

a year ago

341.

XiangShan (香山) is an open-source high-performance RISC-V processor project (github.com/OpenXiangShan)

5 points

4 years ago

342.

We Built UltrafastSecp256k1 Up to 51% Faster ECC Across x86,ARM64,and RISC-V

5 points

3 months ago

343.

MODPlayRISCV – Playing tracker Music on ultra-low-end RISC-V MCUs (github.com/cpldcpu)

5 points

7 months ago

344.

RVVM: RISC-V Virtual Machine (github.com/LekKit)

5 points

a year ago

345.

Release RP2350 and ESP32-C6 support, RISC-V native emitter, common TinyUSB code (github.com/micropython)

5 points

2 years ago

346.

RedFlag: Leveraging AI to find high security risk code changes (github.com/Addepar)

5 points

2 years ago

347.

Ettore: RISC-V virtual machine, written in Go (github.com/teivah)

5 points

2 years ago

348.

SERV – The SErial RISC-V CPU (github.com/olofk)

5 points

2 years ago

349.

A minimal operating system (2K LOC) on QEMU and a RISC-V board (github.com/yhzhang0128)

5 points

3 years ago

350.

core-v-wally: Configurable RISC-V Processor (github.com/openhwgroup)

5 points

3 years ago

351.

Show HN: C++17 RISC-V RV32/64/128 userspace emulator library (github.com/fwsGonzo)

5 points

4 years ago

352.

T-Head/Alibaba RISC-V CPU cores open sourced (github.com/T-head-Semi)

5 points

5 years ago

353.

OpenXiangShan, an open-source high-performance RISC-V processor project (github.com/OpenXiangShan)

5 points

5 years ago

354.

Rvemu: RISC-V Emulator written in Rust (browser and CLI) (github.com/d0iasm)

5 points

5 years ago

355.

Some Criticisms of RISC-V (gist.github.com)

5 points

7 years ago

356.

Opensouce RISC-V CPU core implemented in Verilog from scratch in one night (github.com/darklife)

4 points

a year ago

357.

We went from 13 to 48 tools in our trading risk API for AI agents (github.com/System-R-AI)

4 points

3 months ago

358.

SERV – The SErial RISC-V CPU (github.com/olofk)

4 points

peter_d_sherman

2 years ago

359.

Show HN: Options Trading – Another Quantitative Risk Analysis Software (github.com/aquarians)

4 points

2 years ago

360.

ToolEmu: Identifying the Risks of LM Agents with an LM-Emulated Sandbox (github.com/ryoungj)

4 points

3 years ago