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271.

IceStick Tutorial: experience FPGA design and RISC-V using $40 FPGA device (github.com/BrunoLevy)

119 points

5 years ago

272.

ZipCPU – A small, lightweight, RISC soft core in Verilog (github.com/ZipCPU)

118 points

7 years ago

273.

Hallucination Risk Calculator (github.com/leochlon)

118 points

9 months ago

274.

T1: A RISC-V Vector processor implementation (github.com/chipsalliance)

117 points

a year ago

275.

Show HN: Anos – a hand-written ~100KiB microkernel for x86-64 and RISC-V (github.com/roscopeco)

115 points

2 months ago

276.

De-risking custom technology projects: 18F technology budgeting guide (github.com/18F)

114 points

6 years ago

277.

Jupiter: RISC-V Assembler and Runtime Simulator (github.com/andrescv)

112 points

7 years ago

278.

NanoKVM: Affordable, Multifunctional, Nano RISC-V IP-KVM (github.com/sipeed)

111 points

2 years ago

279.

Leaving Spellcheck Enabled Is a Privacy Risk (2016) (github.com/signalapp)

107 points

6 years ago

280.

Show HN: IDE for Learning RISC-V (github.com/TheThirdOne)

105 points

7 years ago

281.

An FPGA-friendly 32-bit RISC-V CPU implementation (github.com/SpinalHDL)

102 points

9 years ago

282.

VeriGPU: GPU in Verilog loosely based on RISC-V ISA (github.com/hughperkins)

101 points

4 years ago

283.

Open-source soft-core RISC-V SoC with gdb support (github.com/stnolting)

94 points

5 years ago

284.

Multiple Vulnerabilities in IBM Data Risk Manager (github.com/pedrib)

88 points

6 years ago

285.

A minimal operating system (2K LOC) on QEMU and a RISC-V board (github.com/yhzhang0128)

87 points

3 years ago

286.

SiFive open sources RISC-V chips (github.com/sifive)

85 points

10 years ago

287.

QuantMath: Financial maths library for risk-neutral pricing and risk in Rust (github.com/MarcusRainbow)

83 points

5 years ago

288.

Glacial – Microcoded RISC-V core designed for low FPGA resource utilization (github.com/brouhaha)

78 points

peter_d_sherman

5 years ago

289.

ORCA – An implementation of RISC-V intended to target FPGAs (github.com/VectorBlox)

77 points

10 years ago

290.

The Ice-V: a simple, compact RISC-V RV32I implementation in Silice (github.com/sylefeb)

75 points

5 years ago

291.

Show HN: New RISC-V emulator for Computer Science education (github.com/gboncoffee)

71 points

2 years ago

292.

Multiplix, operating system kernel for RISC-V and AArch64 SBCs (github.com/zyedidia)

70 points

3 years ago

293.

Emuko: Fast RISC-V emulator written in Rust, boots Linux (github.com/wkoszek)

70 points

3 months ago

294.

Mojo-V: Secret Computation for RISC-V (github.com/toddmaustin)

66 points

7 months ago

295.

Show HN: A pipelined RISC-V processor written in VHDL (github.com/inforichland)

65 points

11 years ago

296.

Click-V: A RISC-V emulator built with ClickHouse SQL (github.com/SpencerTorres)

64 points

a year ago

297.

Adding custom RISC-V instructions to an open-source rv32 SoC (github.com/stnolting)

54 points

4 years ago

298.

PicoRV32 – A Size-Optimized RISC-V CPU (github.com/cliffordwolf)

53 points

11 years ago

299.

Geohot/twitchcore: A RISC-V core, first in Python, then in Verilog, then on FPGA (github.com/geohot)

51 points

5 years ago

300.

Show HN: I built a RISC-V emulator that runs DOOM (github.com/lalitshankarch)

50 points

a month ago