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1.
▲
C Posix-compliant argument parsing in 42 LoC, inspired by Duff's device
(github.com/camel-cdr)
81 points
camel-cdr
3 years ago
52 comments
2.
▲
Optimizing Brainfuck interpreter in the C preprocessor
(github.com/camel-cdr)
45 points
namanyayg
a year ago
12 comments
3.
▲
RISC-V Vector Extension for Integer Workloads: An Informal Gap Analysis
(gist.github.com)
5 points
camel-cdr
2 years ago
5 comments
4.
▲
Show HN: Advent-of-Code using only the C Preprocessor
(github.com/camel-cdr)
4 points
camel-cdr
3 years ago
1 comment
5.
▲
Show HN: Optimizing brainfuck interpreter using only the C preprocessor
(github.com/camel-cdr)
3 points
camel-cdr
4 years ago
4 comments
6.
▲
A guided (literate) implementation of a random number library
(github.com/camel-cdr)
3 points
camel-cdr
5 years ago
1 comment
7.
▲
Visualizing the RISC-V Instruction Set
(gist.github.com)
3 points
camel-cdr
3 months ago
discuss
8.
▲
Using the Ziggurat Method for Sampling Random Coordinates from a Unit Circle
(gist.github.com)
2 points
camel-cdr
a year ago
discuss
9.
▲
The Improved RISC-V Specification (latest WIP draft)
5 points
camel-cdr
2 years ago
discuss
10.
▲
RISC-V Integrated Matrix Extension Release for Internal Review
(github.com/riscv)
5 points
camel-cdr
3 months ago
discuss
11.
▲
Intel Labs darecreek: open-source RISC-V vector unit (currently under test)
(github.com/IntelLabs)
3 points
camel-cdr
3 years ago
discuss
12.
▲
Preliminary in-progress RISC-V "P" Extension
(github.com/riscv)
2 points
camel-cdr
a month ago
discuss
13.
▲
Singeli – High-level interface for low-level programming
(github.com/mlochbaum)
2 points
camel-cdr
a year ago
discuss
14.
▲
ARM's Scalable Vector Extensions: A Critical Look at SVE2 for Integer Workloads
(gist.github.com)
2 points
camel-cdr
2 years ago
discuss
15.
▲
A simple superscalar out of order RISC-V (micro)processor
(github.com/mathis-s)
2 points
camel-cdr
2 years ago
discuss