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1.

A FPGA friendly 32 bit RISC-V CPU implementation (github.com/SpinalHDL)

121 points

a year ago

2.

An FPGA-friendly 32-bit RISC-V CPU implementation (github.com/SpinalHDL)

102 points

9 years ago

3.

SpinalHDL: Write Scala, Get VHDL/Verilog (github.com/SpinalHDL)

3 points

9 years ago

4.

SpinalHDL – A high level hardware description language based on Scala (github.com/SpinalHDL)

2 points

4 years ago

5.

Advent of Code with SpinalHDL (github.com/fayalalebrun)

1 point

2 years ago