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241.

Packj runner flags risky/malicious NPM/PyPI/Ruby dependencies in your PRs (github.com/marketplace)

2 points

4 years ago

242.

Rvscript: Fast RISC-V-based scripting back end for game engines (github.com/fwsGonzo)

2 points

4 years ago

243.

Adding newlib system calls to a bare-metal RISC-V platform (github.com/stnolting)

2 points

4 years ago

244.

Ripes: Visual computer RISC-V architecture simulator and assembly code editor (github.com/mortbopet)

2 points

4 years ago

245.

Show HN: Superscalar RISC-V CPU written in Clash (github.com/losfair)

2 points

5 years ago

246.

Show HN: Xv6 OS port to Nezha D1 RISC-V board (github.com/michaelengel)

2 points

5 years ago

247.

Show HN: DerzForth – Bare-metal Forth implementation for RISC-V (github.com/theandrew168)

2 points

5 years ago

248.

Rvc – RISC-V in C / HLSL (github.com/PiMaker)

2 points

5 years ago

249.

Open-source RISC-V soft-core NEORV32 adds on-chip debugger support (github.com/stnolting)

2 points

5 years ago

250.

RISC-V Instruction Set Simulator Built for Education (github.com/vmmc2)

2 points

6 years ago

251.

PicoRV32 – A Size-Optimized RISC-V CPU (github.com/cliffordwolf)

2 points

6 years ago

252.

RVScript: Fast RISC-V-based scripting back end for game engines (github.com/fwsGonzo)

2 points

6 years ago

253.

RSD: An Open Source FPGA-Optimized Out-of-Order RISC-V Soft Processor (github.com/rsd-devel)

2 points

6 years ago

254.

LowRISC Ibex – Open Hardware 32-Bit RISC-V CPU with a 2-Stage Pipeline (github.com/lowRISC)

2 points

peter_d_sherman

7 years ago

255.

RISC-V CPU with simple 5-stage in-order pipeline for FPGA (github.com/bluespec)

2 points

8 years ago

256.

PicoRV32 – A Size-Optimized RISC-V CPU (github.com/cliffordwolf)

2 points

11 years ago

257.

ImpactCheck – CLI to detect risky configuration changes before deploy (github.com/fede456)

1 point

4 months ago

258.

The NEORV32 RISC-V soft-core microcontroller (github.com/stnolting)

1 point

5 years ago

259.

Show HN: GodScore CI – a CI gate that blocks risky changes before production (github.com/willshacklett)

1 point

4 months ago

260.

Imagine CUDA on RISC-V (github.com/NVIDIA)

1 point

a year ago

261.

Show HN: rqlite, distributed DB built on SQLite, now runs on MIPS, RISC, PowerPC (github.com/rqlite)

1 point

3 years ago

262.

Run FreeBSD/Aarch64 and FreeBSD/Riscv64 Images Under FreeBSD/Amd64 (gist.github.com)

1 point

4 years ago

263.

Can you hack this RISC-V?

1 point

6 years ago

264.

Fast RISC-V-based scripting backend for game engines (github.com/fwsGonzo)

1 point

6 years ago

265.

Ripes: A graphical processor simulator and assembly editor for the RISC-V ISA (github.com/mortbopet)

1 point

6 years ago

266.

Wujian100_open RISC-V SoC (github.com/T-head-Semi)

1 point

7 years ago

267.

Western Digital’s Open Source RISC-V SweRV Instruction Set Simulator (github.com/westerndigitalcorporation)

1 point

7 years ago

268.

Ucore os was ported on risc-v 32/64 CPU (github.com/chyyuu)

1 point

8 years ago

269.

Tell HN: The Internet situation inside Iran

1045 points

throwaway124592

4 years ago

270.

Ask HN: What weird technical scene are you fond/part of?

295 points

4 years ago