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241.
▲
Show HN: DerzForth – Bare-metal Forth implementation for RISC-V
(github.com/theandrew168)
2 points
theandrew168
5 years ago
discuss
242.
▲
Rvc – RISC-V in C / HLSL
(github.com/PiMaker)
2 points
Cloudef
5 years ago
discuss
243.
▲
Open-source RISC-V soft-core NEORV32 adds on-chip debugger support
(github.com/stnolting)
2 points
_quarks_
5 years ago
discuss
244.
▲
RISC-V Instruction Set Simulator Built for Education
(github.com/vmmc2)
2 points
asicsp
6 years ago
discuss
245.
▲
PicoRV32 – A Size-Optimized RISC-V CPU
(github.com/cliffordwolf)
2 points
dragonsh
6 years ago
discuss
246.
▲
RVScript: Fast RISC-V-based scripting back end for game engines
(github.com/fwsGonzo)
2 points
ingve
6 years ago
discuss
247.
▲
RSD: An Open Source FPGA-Optimized Out-of-Order RISC-V Soft Processor
(github.com/rsd-devel)
2 points
matt_d
6 years ago
discuss
248.
▲
LowRISC Ibex – Open Hardware 32-Bit RISC-V CPU with a 2-Stage Pipeline
(github.com/lowRISC)
2 points
peter_d_sherman
7 years ago
discuss
249.
▲
RISC-V CPU with simple 5-stage in-order pipeline for FPGA
(github.com/bluespec)
2 points
EvgeniyZh
8 years ago
discuss
250.
▲
PicoRV32 – A Size-Optimized RISC-V CPU
(github.com/cliffordwolf)
2 points
jsnell
11 years ago
discuss
251.
▲
The NEORV32 RISC-V soft-core microcontroller
(github.com/stnolting)
1 point
_quarks_
5 years ago
1 comment
252.
▲
Imagine CUDA on RISC-V
(github.com/NVIDIA)
1 point
shifaz
a year ago
discuss
253.
▲
Show HN: rqlite, distributed DB built on SQLite, now runs on MIPS, RISC, PowerPC
(github.com/rqlite)
1 point
otoolep
3 years ago
discuss
254.
▲
Run FreeBSD/Aarch64 and FreeBSD/Riscv64 Images Under FreeBSD/Amd64
(gist.github.com)
1 point
todsacerdoti
4 years ago
discuss
255.
▲
Can you hack this RISC-V?
1 point
delduca
6 years ago
discuss
256.
▲
Fast RISC-V-based scripting backend for game engines
(github.com/fwsGonzo)
1 point
fwsgonzo
6 years ago
discuss
257.
▲
Ripes: A graphical processor simulator and assembly editor for the RISC-V ISA
(github.com/mortbopet)
1 point
lelf
6 years ago
discuss
258.
▲
Wujian100_open RISC-V SoC
(github.com/T-head-Semi)
1 point
fspeech
7 years ago
discuss
259.
▲
Western Digital’s Open Source RISC-V SweRV Instruction Set Simulator
(github.com/westerndigitalcorporation)
1 point
ngaut
7 years ago
discuss
260.
▲
Ucore os was ported on risc-v 32/64 CPU
(github.com/chyyuu)
1 point
chyyuu
8 years ago
discuss
261.
▲
Ask HN: What weird technical scene are you fond/part of?
295 points
ForgotIdAgain
4 years ago
303 comments
262.
▲
Launch HN: Tensil (YC S19) – Open-Source ML Accelerators
96 points
tdba
4 years ago
87 comments
263.
▲
Show HN: StringZilla v3 with C++, Rust, and Swift bindings, and AVX-512 and NEON
(github.com/ashvardanian)
15 points
ashvardanian
2 years ago
10 comments
264.
▲
Show HN: Rucat – Cat for Prompt Engineers
(github.com/brianredbeard)
10 points
thebeardisred
10 months ago
1 comment
265.
▲
DietPi released a new version 8.18
10 points
StephanStS
3 years ago
discuss
266.
▲
Show HN: Stamp – A Cryptographic Identity System
9 points
orthecreedence
5 years ago
5 comments
267.
▲
DietPi released a new version 8.23
9 points
StephanStS
3 years ago
discuss
268.
▲
Show HN: I made a set of tools to write kernel prototypes.
(github.com/glguida)
8 points
tlbflush
a year ago
2 comments
269.
▲
Home-Made RTOS on Renode Simulation
7 points
Eplankton
2 years ago
3 comments
270.
▲
Show HN: GPT Classifies HN Titles
6 points
shagie
3 years ago
4 comments
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