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91.

Show HN: rust-based kernel with asynchronous context switching (github.com/xiaoyang-sde)

1 point

3 years ago

92.

Python RiscV Core (github.com/cjdrake)

2 points

a year ago

93.

Educational OS Labs for RISC-V CPU (github.com/chyyuu)

2 points

8 years ago

94.

An ex-ARM engineer critiques RISC-V (gist.github.com)

350 points

6 years ago

95.

Verilog sources for Western Digital's open source RISC-V core (github.com/westerndigitalcorporation)

320 points

7 years ago

96.

Computerraria: A fully compliant RISC-V computer inside Terraria (github.com/misprit7)

289 points

3 years ago

97.

Open source RISC-V implemented from scratch in one night (github.com/darklife)

272 points

8 years ago

98.

XiangShan – Open-source high performance RISC-V processor (github.com/OpenXiangShan)

270 points

a year ago

99.

Open-source high-performance RISC-V processor (github.com/OpenXiangShan)

262 points

3 years ago

100.

Lion: A formally verified, 5-stage pipeline RISC-V core (github.com/standardsemiconductor)

241 points

5 years ago

101.

Writing an OS in Rust to run on RISC-V (gist.github.com)

229 points

3 years ago

102.

Ariane RISC-V CPU – An open source CPU capable of booting Linux (github.com/openhwgroup)

210 points

6 years ago

103.

Open source RISC-V GPGPU (github.com/vortexgpgpu)

207 points

5 years ago

104.

A tiny C header-only RISC-V emulator (github.com/cnlohr)

205 points

4 years ago

105.

Octox: Unix-like OS in Rust inspired by xv6-riscv (github.com/o8vm)

190 points

3 years ago

106.

Show HN: RISC-V core written in 600 lines of C89 (github.com/mnurzia)

190 points

3 years ago

107.

Linux running inside a PDF file via a RISC-V emulator (github.com/ading2210)

183 points

a year ago

108.

Ariane RISC-V CPU (github.com/pulp-platform)

171 points

8 years ago

109.

Show HN: Minimax – A Compressed-First, Microcoded RISC-V CPU (github.com/gsmecher)

171 points

4 years ago

110.

Fast RISC-V-based scripting back end for game engines (github.com/fwsGonzo)

159 points

2 years ago

111.

A Verilog to Factorio Compiler and Simulator (Working RISC-V CPU) (github.com/ben-j-c)

154 points

2 months ago

112.

Western Digital SweRV RISC-V Core (github.com/chipsalliance)

153 points

6 years ago

113.

Ripes: Visual computer architecture simulator, assembly code editor for RISC-V (github.com/mortbopet)

151 points

3 years ago

114.

LuaJIT PR: Add Support for RISC-V 64 (github.com/LuaJIT)

146 points

2 years ago

115.

Shellfirm: Intercept risky patterns at the command line (github.com/kaplanelad)

145 points

4 years ago

116.

RVVM – The RISC-V Virtual Machine (github.com/LekKit)

140 points

3 years ago

117.

RVVM – RISC-V Virtual Machine (github.com/lekkit)

129 points

5 years ago

118.

Show HN: CLI that spots fake GitHub stars, risky dependencies and licence traps (github.com/m-ahmed-elbeskeri)

122 points

a year ago

119.

A FPGA friendly 32 bit RISC-V CPU implementation (github.com/SpinalHDL)

121 points

a year ago

120.

IceStick Tutorial: experience FPGA design and RISC-V using $40 FPGA device (github.com/BrunoLevy)

119 points

5 years ago