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Top New Best Ask Show Jobs

61.

A Clone of “Space Invaders” in VHDL (github.com/fabioperez)

36 points

10 years ago

62.

Space Invaders Implemented in VHDL Running on an FPGA (github.com/fabioperez)

4 points

10 years ago

63.

Show HN: Verilog HDL support for VS Code (github.com/mshr-h)

3 points

8 years ago

64.

Minecraft HDL, an HDL for Redstone (github.com/itsfrank)

225 points

7 months ago

65.

Microwatt: A tiny Open POWER ISA softcore written in VHDL 2008 (github.com/antonblanchard)

141 points

3 years ago

66.

Show HN: A 16-bit Forth machine written in VHDL (github.com/inforichland)

80 points

12 years ago

67.

A generic VHDL touch controller – add capacitive buttons to any FPGA (github.com/stnolting)

77 points

5 years ago

68.

Microwatt: A Tiny Open Power ISA Softcore Written in VHDL 2008 (github.com/antonblanchard)

73 points

7 years ago

69.

Show HN: A pipelined RISC-V processor written in VHDL (github.com/inforichland)

65 points

11 years ago

70.

Forth SoC Written in VHDL (github.com/howerj)

54 points

5 years ago

71.

SystemLisp – an HDL simulator written in Common Lisp (github.com)

15 points

2 months ago

72.

NVC: VHDL Compiler and Simulator (github.com/nickg)

8 points

a year ago

73.

Show HN: High performance VHDL based ADS-B decoder (github.com/Nuand)

5 points

10 years ago

74.

Geode: A Classic 5-Stage Pipeline Written in Atlas/Python HDL (github.com/medav)

4 points

8 years ago

75.

A SAT solver implementation in VHDL, welcome feedback (github.com/Sumith1896)

4 points

10 years ago

76.

Show HN: Click-Flasher, a simple FPGA design written in VHDL (github.com/brakmic)

4 points

10 years ago

77.

PipelineC: A C-like HDL adding automatic pipelining (github.com/JulianKemmerer)

3 points

6 years ago

78.

p-Vex: A Reconfigurable and Extensible [FPGA, 32-Bit] VLIW Soft Processor (VHDL) (github.com/tvanas)

3 points

peter_d_sherman

7 years ago

79.

Microwatt – A Tiny Open Power ISA Softcore Written in VHDL 2008 (github.com/antonblanchard)

3 points

7 years ago

80.

SpinalHDL: Write Scala, Get VHDL/Verilog (github.com/SpinalHDL)

3 points

9 years ago

81.

New PyXHDL Release (Python Frontend To VHDL And Verilog) (github.com/davidel)

2 points

a month ago

82.

PyXHDL – Python Front End for VHDL and Verilog (github.com/davidel)

2 points

2 months ago

83.

Sparkle HDL (github.com/Verilean)

2 points

2 months ago

84.

C++ HDL (Hardware Description Language) (github.com/mirekez)

2 points

6 months ago

85.

Show HN: An efficient SRL32 (cascading shift registers) clock prescaler in VHDL (gist.github.com)

2 points

2 years ago

86.

Chisel: a scala based HDL using layered domain-specific hardware languages (github.com/ucb-bar)

1 point

13 years ago

87.

Polymorphic Blocks – WIP HDL (github.com/BerkeleyHCI)

1 point

3 years ago

88.

PCBFlow – Transform VHDL/Verilog to a Discrete Circuit on a PCB (github.com/cpldcpu)

1 point

5 years ago

89.

My first steps into VHDL/FPGAs – real-time fractal zooming (github.com/ttsiodras)

1 point

7 years ago

90.

Show HN: Game Bub – open-source FPGA retro emulation handheld (eli.lipsitz.net)

274 points

a year ago