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571.
▲
Smol-GPU: A tiny RISC-V GPU built to teach modern GPU architecture
(github.com/Grubre)
8 points
thunderbong
a year ago
discuss
572.
▲
How to get started with Rust for RISC-V targets
(github.com/ockam-network)
8 points
__mrinal__
5 years ago
discuss
573.
▲
Linux on RISC-V on Arduino Uno
(github.com/raspiduino)
7 points
jamesy0ung
3 years ago
6 comments
574.
▲
Kilo editor ported to Forth for RISC-V
(github.com/mcmenaminadrian)
7 points
00_NOP
a year ago
4 comments
575.
▲
Apple is adding Mach-O's riscv32 support to LLVM
(github.com/llvm)
7 points
MaskRay
a year ago
1 comment
576.
▲
D Apps for Apache NuttX RTOS and QEMU RISC-V
(github.com/kassane)
7 points
lupyuen
2 years ago
discuss
577.
▲
Muntjac: An open source, Linux capable, 64 bit RISCV core
(github.com/lowRISC)
7 points
gchadwick
4 years ago
discuss
578.
▲
Show HN: Bronzebeard – Minimal assembler for bare-metal RISC-V development
(github.com/theandrew168)
7 points
theandrew168
5 years ago
discuss
579.
▲
JuiceVM: Smallest RISC-V Virtual Machine that can run Linux mainline kernel
(github.com/juiceRv)
7 points
homarp
5 years ago
discuss
580.
▲
BinSym: Symbolic execution for RISC-V machine code based on LibRISCV ISA model
(github.com/agra-uni-bremen)
6 points
matt_d
2 years ago
discuss
581.
▲
CVA6 – an Application class 6-stage RISC-V CPU capable of booting Linux
(github.com/openhwgroup)
6 points
rwmj
3 years ago
discuss
582.
▲
FreeBSD Adapted for Cheri-MIPS, Cheri-RISC-V, and Arm Morello
(github.com/CTSRD-CHERI)
6 points
lsllc
5 years ago
discuss
583.
▲
Flute: RISC-V CPU, simple 5-stage in-order pipeline
(github.com/bluespec)
6 points
EvgeniyZh
7 years ago
discuss
584.
▲
RISC-V Vector Extension for Integer Workloads: An Informal Gap Analysis
(gist.github.com)
5 points
camel-cdr
2 years ago
5 comments
585.
▲
Show HN: RISC-V Linux Terminal emulated via WASM
(cartesi-machine.surge.sh)
5 points
edubart
3 years ago
5 comments
586.
▲
Show HN: Brainfuck to RISC-V JIT compiler written in Zig
(github.com/evelance)
5 points
0x000xca0xfe
a year ago
3 comments
587.
▲
XiangShan (香山) is an open-source high-performance RISC-V processor project
(github.com/OpenXiangShan)
5 points
DeathArrow
4 years ago
1 comment
588.
▲
We Built UltrafastSecp256k1 Up to 51% Faster ECC Across x86,ARM64,and RISC-V
5 points
shrecshrec
4 months ago
discuss
589.
▲
MODPlayRISCV – Playing tracker Music on ultra-low-end RISC-V MCUs
(github.com/cpldcpu)
5 points
cpldcpu
7 months ago
discuss
590.
▲
RVVM: RISC-V Virtual Machine
(github.com/LekKit)
5 points
api
a year ago
discuss
591.
▲
Release RP2350 and ESP32-C6 support, RISC-V native emitter, common TinyUSB code
(github.com/micropython)
5 points
rcarmo
2 years ago
discuss
592.
▲
Ettore: RISC-V virtual machine, written in Go
(github.com/teivah)
5 points
ingve
2 years ago
discuss
593.
▲
SERV – The SErial RISC-V CPU
(github.com/olofk)
5 points
RossBencina
2 years ago
discuss
594.
▲
A minimal operating system (2K LOC) on QEMU and a RISC-V board
(github.com/yhzhang0128)
5 points
Paul-Craft
3 years ago
discuss
595.
▲
core-v-wally: Configurable RISC-V Processor
(github.com/openhwgroup)
5 points
matt_d
3 years ago
discuss
596.
▲
Show HN: C++17 RISC-V RV32/64/128 userspace emulator library
(github.com/fwsGonzo)
5 points
fwsgonzo
4 years ago
discuss
597.
▲
T-Head/Alibaba RISC-V CPU cores open sourced
(github.com/T-head-Semi)
5 points
johndoe0815
5 years ago
discuss
598.
▲
OpenXiangShan, an open-source high-performance RISC-V processor project
(github.com/OpenXiangShan)
5 points
bctnry
5 years ago
discuss
599.
▲
Rvemu: RISC-V Emulator written in Rust (browser and CLI)
(github.com/d0iasm)
5 points
ansible
5 years ago
discuss
600.
▲
Some Criticisms of RISC-V
(gist.github.com)
5 points
fanf2
7 years ago
discuss
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