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481.
▲
Show HN: Emacs-riscv – A RISC-V emulator written in Emacs Lisp
(github.com/gongo)
10 points
gongo
5 months ago
discuss
482.
▲
Marss-Riscv: Micro-ARchitectural Full System Simulator for RISC-V
(github.com/bucaps)
8 points
GeorgeTirebiter
7 years ago
1 comment
483.
▲
Riscrithm (v1.1) – An intuitive RISC-V assembler and optimizer written in Go
(github.com/ghetea-patrick)
4 points
patrick-ghetea
4 days ago
2 comments
484.
▲
RISC-V Vector Primer
(github.com/simplex-micro)
4 points
mshockwave
4 months ago
discuss
485.
▲
Calyx-riscv: RISCV Core written in Calyx
(github.com/sgpthomas)
4 points
luu
2 years ago
discuss
486.
▲
A concise example for learning assembly, linking and relocation
(github.com/peiyuanix)
4 points
peiyuanix
3 years ago
discuss
487.
▲
A minimal RISC-V bare metal program to print “Hello, RISC-V”
(github.com/peiyuanix)
4 points
peiyuanix
3 years ago
discuss
488.
▲
Jonesforth Port to RISC-V
(github.com/jjyr)
2 points
rwmj
6 years ago
1 comment
489.
▲
Show HN: Porting RISCOF to a new RISC-V target
(github.com/stnolting)
2 points
youre_the_voice
4 years ago
discuss
490.
▲
Porting OpenBSD to RISC-V ISA
(github.com/MengshiLi)
2 points
gbrown_
5 years ago
discuss
491.
▲
Show HN: A small RISC-V Virtual Machine
(github.com/bit-hack)
2 points
bit-hack
6 years ago
discuss
492.
▲
Port of (JavaScript version of) corewars8086 to RISC-V
(github.com/westerndigitalcorporation)
2 points
harshreality
7 years ago
discuss
493.
▲
RISC-V CPU in Chisel
(github.com/ucb-bar)
1 point
electronous
13 years ago
discuss
494.
▲
Show HN: The C3 programming language (C alternative language)
(github.com/c3lang)
175 points
lerno
a year ago
185 comments
495.
▲
Ask HN: Examples of Microkernels?
80 points
agomez314
4 years ago
79 comments
496.
▲
Vibe Code Warning – A personal casestudy
(github.com/jackdoe)
400 points
jackdoe
7 months ago
313 comments
497.
▲
Xv6 for RISC-V
(github.com/mit-pdos)
114 points
ingve
7 years ago
8 comments
498.
▲
RISC-V userspace emulator library
(github.com/fwsGonzo)
43 points
ingve
7 years ago
4 comments
499.
▲
Xv6 for RISC-V
(github.com/mit-pdos)
5 points
tirrex
4 years ago
discuss
500.
▲
RISC-V userspace emulator library
(github.com/fwsGonzo)
3 points
ingve
7 years ago
discuss
501.
▲
How to make RISC-V Microcomputer using FPGA for programmer
(github.com/horie-t)
2 points
teleforce
4 years ago
1 comment
502.
▲
Show HN: TCP Socket in RISC-V Assembly (RV64I)
(github.com/triilman25)
4 points
triilman
a year ago
discuss
503.
▲
AOSP (Android 10) port to RISC-V
(github.com/T-head-Semi)
4 points
rwmj
5 years ago
discuss
504.
▲
Android 10 ported to RISC-V
(github.com/T-head-Semi)
2 points
varbhat
5 years ago
discuss
505.
▲
Show HN: rust-based kernel with asynchronous context switching
(github.com/xiaoyang-sde)
1 point
xasiimov
3 years ago
1 comment
506.
▲
Python RiscV Core
(github.com/cjdrake)
2 points
vortexfever
a year ago
discuss
507.
▲
Educational OS Labs for RISC-V CPU
(github.com/chyyuu)
2 points
chyyuu
8 years ago
discuss
508.
▲
An ex-ARM engineer critiques RISC-V
(gist.github.com)
350 points
ducktective
6 years ago
249 comments
509.
▲
Verilog sources for Western Digital's open source RISC-V core
(github.com/westerndigitalcorporation)
320 points
obl
7 years ago
78 comments
510.
▲
Computerraria: A fully compliant RISC-V computer inside Terraria
(github.com/misprit7)
289 points
inickt
3 years ago
41 comments
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