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451.

No-MMU Linux Capable RISC-V SoC (github.com/regymm)

2 points

4 years ago

452.

The CORE-V CVA6 is a RISC-V CPU capable of booting Linux (github.com/openhwgroup)

2 points

4 years ago

453.

Packj runner flags risky/malicious NPM/PyPI/Ruby dependencies in your PRs (github.com/marketplace)

2 points

4 years ago

454.

Rvscript: Fast RISC-V-based scripting back end for game engines (github.com/fwsGonzo)

2 points

4 years ago

455.

Adding newlib system calls to a bare-metal RISC-V platform (github.com/stnolting)

2 points

4 years ago

456.

Ripes: Visual computer RISC-V architecture simulator and assembly code editor (github.com/mortbopet)

2 points

4 years ago

457.

Show HN: Superscalar RISC-V CPU written in Clash (github.com/losfair)

2 points

5 years ago

458.

Show HN: Xv6 OS port to Nezha D1 RISC-V board (github.com/michaelengel)

2 points

5 years ago

459.

Show HN: DerzForth – Bare-metal Forth implementation for RISC-V (github.com/theandrew168)

2 points

5 years ago

460.

Rvc – RISC-V in C / HLSL (github.com/PiMaker)

2 points

5 years ago

461.

Conquest – Risk-like game written in Godot (github.com/argosopentech)

2 points

5 years ago

462.

Open-source RISC-V soft-core NEORV32 adds on-chip debugger support (github.com/stnolting)

2 points

5 years ago

463.

Git by a Bus: Estimate unique and at-risk knowledge in your source code (github.com/tomheon)

2 points

5 years ago

464.

RISC-V Instruction Set Simulator Built for Education (github.com/vmmc2)

2 points

6 years ago

465.

PicoRV32 – A Size-Optimized RISC-V CPU (github.com/cliffordwolf)

2 points

6 years ago

466.

Open source API to evaluate risk of Covid-19 contamination during a trip (github.com/thetreep)

2 points

6 years ago

467.

RVScript: Fast RISC-V-based scripting back end for game engines (github.com/fwsGonzo)

2 points

6 years ago

468.

RSD: An Open Source FPGA-Optimized Out-of-Order RISC-V Soft Processor (github.com/rsd-devel)

2 points

6 years ago

469.

LowRISC Ibex – Open Hardware 32-Bit RISC-V CPU with a 2-Stage Pipeline (github.com/lowRISC)

2 points

peter_d_sherman

7 years ago

470.

De-risking custom technology projects (github.com/18F)

2 points

7 years ago

471.

RISC-V CPU with simple 5-stage in-order pipeline for FPGA (github.com/bluespec)

2 points

8 years ago

472.

Method for an Optimised aNAlysis of Risks version 2.7.1 released (github.com/monarc-project)

2 points

8 years ago

473.

MONARC introduces the Statement of Applicability module for your risk analysis (github.com/monarc-project)

2 points

8 years ago

474.

Show HN: FireCaster – Predicting Urban Fire Risk in NYC (github.com/tzano)

2 points

8 years ago

475.

Reduce your risk of RSI when using Redux (github.com/civicsource)

2 points

10 years ago

476.

PicoRV32 – A Size-Optimized RISC-V CPU (github.com/cliffordwolf)

2 points

11 years ago

477.

Pyfolio – a Python library for financial performance and risk analysis (github.com/quantopian)

2 points

11 years ago

478.

ImpactCheck – CLI to detect risky configuration changes before deploy (github.com/fede456)

1 point

4 months ago

479.

Show HN: PreApply – Terraform plan analyzer with blast radius and risk scoring (github.com/akileshthuniki)

1 point

4 months ago

480.

Show HN: At Your Own Risk – Disclaimer pages for things that don't need them (atyourownri.sk)

1 point

2 months ago