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451.

Need Suggestions for Riscv CPU (github.com/SHAOWEICHEN000)

2 points

a year ago

452.

Command-Line Lint (github.com/riscy)

2 points

7 years ago

453.

Excellent Project Documentation (github.com/RISCfuture)

2 points

13 years ago

454.

Preliminary in-progress RISC-V "P" Extension (github.com/riscv)

2 points

a month ago

455.

Prototype of Telekom Developergarden API Client for nodejs (github.com/grischaandreew)

2 points

14 years ago

456.

Jquery.couch.extended.js (github.com/grischaandreew)

2 points

14 years ago

457.

RISC-V Architecture Profiles 0.5 (RVI20, RVA20 and RVA22) for Discussion (github.com/riscv)

2 points

4 years ago

458.

Digital Signatures on Risc0 (github.com/risc0)

2 points

4 years ago

459.

PyTips: A curated listing of Python examples by Mike Driscoll (github.com/driscollis)

2 points

5 years ago

460.

ELF Reader in Pure Tcl (github.com/jbroll)

2 points

5 years ago

461.

riscv-pk: RISC-V Proxy Kernel and Boot Loader (github.com/riscv)

2 points

6 years ago

462.

New open source F# RISC-V ISA formal specification and CPU simulation (github.com/mrLSD)

2 points

7 years ago

463.

Working draft of the proposed RISC-V V vector extension (github.com/riscv)

1 point

2 years ago

464.

RISC Zero MCP Server: Run Trustless and Verifiable Agentic Workflows (github.com/ronantakizawa)

1 point

10 months ago

465.

Concerns over mask register design in RISC-V Vector Extension v1.0 (github.com/riscv)

1 point

4 years ago

466.

Squall: A TUI SQLite Viewer and Editor (github.com/driscollis)

1 point

a year ago

467.

Show HN: Random instruction generator for RISC-V processor verification (github.com/google)

1 point

5 years ago

468.

F# RISC-V Instruction Set Formal Specification (github.com/mrLSD)

1 point

7 years ago

469.

Application execution environment for statically-linked RISC-V ELF binaries (github.com/riscv)

1 point

7 years ago

470.

RISC vs. Cores and SoCs (github.com/riscv)

1 point

7 years ago

471.

Show HN: I integrated my from-scratch TCP/IP stack into the xv6-riscv OS (github.com/pandax381)

147 points

9 months ago

472.

Show HN: Porting xv6 to HiFive Unmatched board (github.com/eyengin)

26 points

5 months ago

473.

Show HN: Easier Setup for Stephen Marz's “RISC-V OS in Rust” Series (github.com/kaycebasques)

3 points

3 years ago

474.

Project Oberon 2013 on RISC-V (github.com/solbjorg)

140 points

5 years ago

475.

Show HN: Confidential computing for high-assurance RISC-V embedded systems (github.com/IBM)

103 points

a year ago

476.

Porting OpenBSD to RISC-V Final Report (2020) [pdf] (github.com/MengshiLi)

93 points

5 years ago

477.

RISC-V Vector Primer (github.com/simplex-micro)

69 points

4 months ago

478.

Jonesforth Port to RISC-V (github.com/jjyr)

66 points

5 years ago

479.

Riscrithm – An intuitive RISC-V assembler and optimizer coded in Go (github.com/ghetea-patrick)

32 points

12 days ago

480.

RiscVivid – An educational RISC-V simulator (github.com/unia-sik)

14 points

4 years ago