The core idea: hardware design tools throw away too much intent too early. You write a state machine, but by the time it hits synthesis, the tool only sees a bag of gates and has to reverse-engineer what you meant. SKALP keeps that intent through four intermediate representations — from a high-level algorithmic IR down to gate-level netlist — so each compilation stage has the context it needs to make good decisions.

The thing I'm most interested in technically is clock domain crossings as compile-time types. If you've worked on multi-clock designs, you know CDC bugs are some of the hardest to find. In SKALP, clock domains are parameterized types (think Rust lifetimes but for clocks), so connecting signals across domains without a proper synchronizer is a compiler error, not a simulation surprise at 3am.

Other pieces that might be interesting: GPU-accelerated fault simulation via Metal (~11M fault-cycle sims/sec on M4 Max), integrated P&R targeting iCE40 FPGAs, built-in formal verification, and ISO 26262 FMEDA generation. There's also a VSCode extension with an integrated waveform viewer, a debug adapter with cycle-level stepping and conditional breakpoints, and testbench integration through the test explorer. The syntax is expression-based and Rust-influenced — traits, generics, pattern matching.

It's still early. The iCE40 backend works but coverage is limited, and the GPU path is macOS-only for now. The codebase is ~290K lines across 23 crates.

  Website: https://mikaana.com/projects/skalp/
  GitHub: https://github.com/girivs82/skalp
  Tutorial (10 chapters): https://mikaana.com/tutorial/
  Blog post on the IR pipeline: https://mikaana.com/blog/skalp-ir-pipeline/