I'm here to share a project I've been working on for the past 4 days, though I've mulled over the core logic for years. I deeply share the values of this community, I’ve mostly stayed in the shadows.

I’ve reached a point where the results feel significant: ~3,200+ RPS sustained on bare metal with zero allocation and 1:1 IR-to-native mapping, yet with hardware-enforced memory safety. I’m moving the "Safety Tax" from the CPU's hot-path to a load-time formal verification step.

I’ve put together a README and some forensic artifacts (CBMB headers, SCEV audit traces, and 1:1 assembly mappings) to prove this isn't just theory.

Please go to https://github.com/pratyagatma/skl.git and review the artifacts, https://streamable.com/emxwvu for demo. Any feedback—especially from those who hate "abstraction bloat" as much as I do—is much appreciated.

10-40KB event loop sevaka implementation coming soon!

Thanks.